2017vlsi3

UNIST ECE graduate students’ paper accepted at VLSI Symposium 2017

Activities March 23, 2017

 

ICSL’s paper (authors: Taeho Seong, Yongsun Lee, Seyeon Yoo, and Prof. Jaehyouk Choi) “A -242dB FOM and -71dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL” has been accepted for presentation at the forthcoming Symposium on VLSI Circuits 2017 which will be held in Tokyo.

 

Symposium on VLSI Circuits is one of the three major conferences on semiconductor circuits, along with ISSCC(International Solid-State Circuits Conference) and CICC(Custom Integrated Circuits Conference). In this paper, an ultra-low jitter, low-reference spur switched-loop-filter PLL was presented. The prototype circuit was fabricated using a TSMC 65-nm CMOS process.

 

Authors: Taeho Seong, Yongsun Lee, Seyeon Yoo, and Jaehyouk Choi

Title: A -242dB FOM and -71dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL

Conference: 2017 IEEE Symposium on VLSI Circuits

Accept rate: < 30%

Presentation date: June, 2017