20151020_최재혁교수님_

A 185-fsrms Integrated-Jitter and –245-dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier

Seojin Choi, Seyeon Yoo, and Jaehyouk Choi’s paper “A 185-fsrms Integrated-Jitter and –245-dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier” has been accepted for presentation at 2016 IEEE ISSCC (International Solid-State Circuits Conference) in February in San Francisco. ISSCC is called “the Olympic in the field of semiconductor circuit designs” and acknowledged as the single most prestigious conference in this field.

In this work, a new ring-VCO-based clock generator is presented to overcome major drawbacks of conventional injection-locked clock multipliers. Using the proposed ring-VCO-based calibrator, the VCO can track the frequency change over real-time environmental variations, while also achieved ultra-low jitter performance. The clock multiplier was fabricated in a 65-nm CMOS technology, and the active area was 0.06 mm2.

 

Authors: Seojin Choi, Seyeon Yoo, and Jaehyouk Choi

Title: A 185-fsrms Integrated-Jitter and –245-dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier

Conference: 2016 IEEE International Solid-State Circuit Conference (ISSCC)

Accept rate: < 20%

Presentation date: February, 2016