UNIST ECE students’ paper accepted at DATE 2018
SoCDL’s paper (authors: Seungwon Kim, Prof. Ki Jin Han, Prof. Youngmin Kim and Prof. Seokhyeong Kang) “Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-Domain High-Speed Memory: A Case Study” has been accepted for presentation at 2018 21st DATE (Design, Automation and Test in Europe) in Dresden, Germany in coming March.
DATE is one of the top conference in the field of EDA (Electronic Design Automation). In this paper, proposed chip-package-PCB coanalysis methodology, which applied to our multi-domain high-speed memory system model with a current generation method.
Proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPDDR4 environment.
Authors: Seungwon Kim, Ki Jin Han, Youngmin Kim and Seokhyeong Kang
Title: Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-Domain High-Speed Memory: A Case Study
Conference: 2018 21st Design, Automation and Test in Europe (DATE)
Presentation date: TBD