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One ICSL’s paper accepted to JSSC 2019

Activities, News January 15, 2019

An Ultra-Low Jitter Multi-Frequency Generator Using Time-Interleaved Calibration and An Injection Locking for Modern System-on-Chips (SoCs)
The authors: Heein Yoon (First author) and Suneui Park in the Ph.D. program of ECE (From the left side)

ICSL’s paper, “A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration” has been accepted for publication in IEEE Journal of Solid-State Circuits, which is the most prestigious journal in the field of semiconductor circuits. The authors are Heein Yoon, Suneui Park, and Jaehyouk Choi*.

 

In this paper, Heein presents a low jitter, highly digital injection-locked frequency generator that can provide multiple output frequencies, concurrently. The proposed frequency calibrator operating in a time-interleaved manner can continue to correct the multiple output frequencies of the DCOs in a real-time fashion. Since it uses one common frequency calibrator, as the number of DCO increases the area and power efficiency of the proposed frequency generator are improved more, while maintaining excellent jitter performance. The proposed frequency generator was fabricated in 65-nm CMOS technology, and the active area was 0.05 mm2. The total power consumption was 7.74 mW to generate two different output frequencies.

 

Article Title: A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally-Controlled Oscillators and Time-Interleaved Calibration

 

Authors: Heein Yoon, Suneui Park, and Jaehyouk Choi

 

Journal Title: IEEE Journal of Solid-State Circuits (JSSC)

 

IF: 4.075