UNIST ECE students’ paper accepted at ASP-DAC 2018
SoCDL’s paper (authors: Sunmean Kim, Taeho Lim and Prof. Seokhyeong Kang) “Optimal Static Gate Design for Synthesis of Ternary Logic Circuits” has been accepted for presentation at 2018 23rd IEEE/ACM ASP-DAC (Asia and South Pacific Design Automation Conference) in Jeju, Korea in coming January.
ASP-DAC is one of the top conferences in the field of EDA (Electronic Design Automation). This paper proposed an optimal static gate design methodology for the synthesis of ternary logic using emerging devices.
Proposed ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. In addition, the ternary multiplier shows the smaller number of the transistor over the binary multiplier, especially on the large digit size.
Authors: Sunmean Kim, Taeho Lim and Seokhyeong Kang
Title: Optimal Static Gate Design for Synthesis of Ternary Logic Circuits
Conference: 2018 23rd IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
Presentation date: TBD