20151102

Super-clean Clock Generation for Semiconductor Chips

ICSL (Prof. Jaehyouk Choi)’s paper “A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay” has been accepted for publication in IEEE Journal of Solid-State Circuits (Authors: Mina Kim, Seojin Choi, Taeho Seong, and jaehyouk Choi).

In this paper, the DLL-based PVT calibrator was proposed to overcome major drawbacks of conventional injection-locked clock multipliers. Using the proposed DLL-based calibrator, this work achieved both capabilities of a fractional resolution and a real-time PVT-calibration. The clock multiplier was fabricated in a 65-nm CMOS technology, and the active area was 0.041 mm2.

Article title: A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-time PVT-Calibrator with Replica-Delay

Authors: Mina Kim, Seojin Choi, Taeho Seong, and jaehyouk Choi

Journal title : IEEE Journal of Solid-State Circuits (JSSC)

IF: 3.009 (9.2%) / AIS: 1.603 (6.4%), JCR 2014