사진(최재혁)-150521

A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells

Mina Kim, Seojin Choi, and Jaehyouk Choi’s paper “A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells” is accepted for presentation at the forthcoming Symposium on VLSI Circuits 2015 held in Kyoto. In this paper, the DLL-based PVT calibrator is proposed to overcome major drawbacks of conventional injection locked clock multipliers. Using the proposed DLL-based calibrator, the VCO can track the frequency change over real-time environmental variations. Also, this clock multiplier achieved a fine frequency resolution by rotationally switching the injecting point of the multi-stage VCO. The clock multiplier was fabricated in a 65-nm CMOS technology, and the active area was 0.041 mm2.

 

Authors: Mina Kim, Seojin Choi, and Jaehyouk Choi

Title: A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells

Conference: IEEE Symposium on VLSI Circuits

Acceptance ratio: < 30%

Presentation date: June 15th, 2015

Symposium on VLSI Circuits is the one of the top 3 conferences in the field of integrated circuit (IC) designs.